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DATA SHEET
MOS INTEGRATED CIRCUIT
PD8821
7300 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The PD8821 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The PD8821 has 3 rows of 7300 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge transfer register, which transfers the photo signal electrons of 7300 pixels separately in odd and even pixels. Therefore, it is suitable for 600dpi/A3 high-speed color digital copiers, color scanners and so on by the use of the package with heat sink that has high heat radiation.
FEATURES
* Valid photocell * Photocell pitch * Line spacing * Color filter * Resolution * Data rate * Output type * Power supply * Drive clock level * On-chip circuits : 7300 pixels x 3 : 10 m : 40 m (4 lines) Red line-Green line, Green line-Blue line : 24 dot/mm A3 (297 x 420 mm) size (shorter side) : 60 MHz MAX. (30 MHz/ch max.) : 2 outputs in phase/color : +10 V : CMOS output under 5 V operation : Reset feed-through level clamp circuit Voltage amplifiers : Primary colors (red, green, and blue), pigment filter (with 10 lx*hour tolerant)
7
ORDERING INFORMATION
Part Number Package CCD linear image sensor 40-pin plastic DIP with heat sink (15.24 mm (600))
PD8821CZ-A
Remark
The PD8821CZ-A is a lead-free product.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. S17961EJ2V0DS00 (2nd edition) Date Published July 2007 NS Printed in Japan
The mark shows major revised points. The revised points can be easily searched by copying an "" in the PDF file and specifying it in the "Find what:" field.
2006
PD8821
BLOCK DIAGRAM
CP
35
2L
34
GND
33
1BO
32
2AO
31
1B
25
2A
26
VOD
36
VOUT2 (Blue, even)
37
CCD analog shift register Transfer gate S7299 D128 D27 S1 S2
...
D129
...
D140
Photocell (Blue)
S7300
24
Transfer gate VOUT1 (Blue, odd) GND
39 38
TG1
CCD analog shift register
VOUT3 (Green, odd)
40
CCD analog shift register Transfer gate S7299 D128 D27 S1 S2
...
D129
...
D140
Photocell (Green)
S7300
23
Transfer gate VOUT4 (Green, even) GND VOUT6 (Red, even) D128 D27 S1
2 18 1
TG2
CCD analog shift register GND
3
CCD analog shift register Transfer gate S7299 S2
...
...
D140
D129
Photocell (Red)
S7300
17
Transfer gate VOUT5 (Red, odd)
4
TG3
CCD analog shift register
5
6
7
8
9
10
15
16
VOD
R
2L
GND
2BO
1AO
11 30
1A
2B
HS-VOD
HS-VOD
2
Data Sheet S17961EJ2V0DS
PD8821
PIN CONFIGURATION (Top View)
CCD linear image sensor 40-pin plastic DIP with heat sink (15.24 mm (600))
PD8821CZ-A
Output signal 4 (Green-even) Ground Output signal 6 (Red-even) Output signal 5 (Red-odd) Output unit drain voltage 2 Reset gate clock Last stage shift register clock Ground Shift register clock 2BO Shift register clock 1AO
1 2 3 4 5 6 7 8 9 10
VOUT4 GND VOUT6 VOUT5 VOD 1 1 1
VOUT3 GND VOUT1 VOUT2 VOD
40 39 38 37 36 35 34 33 32 31
Output signal 3 (Green-odd) Ground Output signal 1 (Blue-odd) Output signal 2 (Blue-even) Output unit drain voltage Reset feed-through level clamp clock Last stage shift register clock Ground Shift register clock 1BO Shift register clock 2AO
R 2L
GND
CP 2L
GND
2BO 1AO
Green Blue Red
1BO 2AO
Package Heat-Sink VOD No connection No connection No connection Shift register clock 1A Shift register clock 2B Transfer gate clock 3 Ground No connection No connection
11 12 13 14 15 16 17 18 19 20
HS-VOD NC NC NC
HS-VOD NC NC NC
30 29 28 27 26 25 24 23 22 21
Package Heat-Sink VOD No connection No connection No connection Shift register clock 2A Shift register clock 1B Transfer gate clock 1 Transfer gate clock 2 No connection No connection
1A 2B TG3
7300 7300 7300 GND NC NC
2A 1B TG1 TG2
NC NC
Caution
Pins 11 and 30 (HS-VOD) are connected only to the heat sink. These pins are not connected to VOD (pins 5 or 36) inside this device. Set HS-VOD (pins 11 and 30) to VOD (pins 5 and 36) in common on a board. Each VOD is connected inside this device.
PHOTOCELL STRUCTURE DIAGRAM
7 m 10 m
3 m
Channel stopper
Aluminum shield
Data Sheet S17961EJ2V0DS
3
PD8821
ABSOLUTE MAXIMUM RATINGS (TA = +25C)
Parameter Output drain voltage Heat sink voltage Shift register clock voltage Last stage shift register clock voltage Reset gate clock voltage Reset feed-through level clamp clock voltage Transfer gate clock voltage Operating ambient temperature Note Storage temperature VOD HS-VOD V 1, V 2 V 2L V R V CP V TG1 to V TG3 TA Tstg Symbol Ratings -0.3 to +12.0 -0.3 to +12.0 -0.3 to +8.0 -0.3 to +8.0 -0.3 to +8.0 -0.3 to +8.0 -0.3 to +8.0 0 to +60 -40 to +100 Unit V V V V V V V C C
Note
The operating ambient temperature is defined as an atmosphere temperature in a point 10 mm away on the substrate, and 10 mm away from the short side of package 1 pin.
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25C)
Parameter Output drain voltage Heat sink voltage Shift register clock high level Shift register clock low level Last stage shift register clock high level Last stage shift register clock low level Reset gate clock high level Reset gate clock low level Reset feed-through level clamp clock high level Reset feed-through level clamp clock low level Transfer gate clock high level Note Transfer gate clock low level Shift register clock amplitude Last stage shift register clock amplitude Reset gate clock amplitude Reset feed-through level clamp clock amplitude Transfer gate clock amplitude Data rate VOD HS-VOD V 1H, V 2H V 1L, V 2L V 2LH V 2LL V RH V RL V CPH V CPL V TG1H to V TG3H V TG1L to V TG3L V 1p-p, V 2p-p V 2Lp-p V Rp-p V CPp-p V TGp-p 2 x f R Symbol MIN. 9.5 9.5 4.75 -0.3 4.75 -0.3 4.75 -0.3 4.75 -0.3 4.75 -0.3 4.75 4.75 4.75 4.75 4.5 0.2 TYP. 10.0 10.0 5.0 0.0 5.0 0.0 5.0 0.0 5.0 0.0 V 1H 0.0 5.0 5.0 5.0 5.0 5.0 2 MAX. 10.5 10.5 6.0 +0.25 6.0 +0.25 5.5 +0.5 6.0 +0.5 V 1H +0.5 6.3 6.3 6.3 6.3 6.3 60 Unit V V V V V V V V V V V V V V V V V MHz
Note
When Transfer gate clock high level (V TGH) is higher than shift register clock high level (V 1H), image lag can increase.
4
Data Sheet S17961EJ2V0DS
PD8821
ELECTRICAL CHARACTERISTICS
TA = +25C, VOD = +10 V, f R = 1 MHz, data rate = 2 MHz, storage time = 10 ms, input clock = 5 Vp-p
light source (except Response2): 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm)+ HA-50 (heat absorbing filter, t = 3 mm)
Parameter Saturation voltage
Symbol Vsat Red Green Blue SER SEG SEB PRNU ADS DSNU PW ZO Red Green Blue RR RG RB
Test Conditions
MIN. 1.2
TYP. 1.5 0.15 0.19 0.35 6.0 1.0 2.0 640 0.2 9.8 7.9 4.3 610 535 460 1.0 4.5 7.0 0 98 750 3000 -200 -200 0.5
MAX. - - - - 18.0 5.0 10.0 740 0.4 12.74 10.27 5.59 - - - 5.0 5.5 8.0 4 - - - +500 +500 -
Unit V lx*s lx*s lx*s % mV mV mW k V/lx*s V/lx*s V/lx*s nm nm nm % V ns % % times times mV mV mV

Saturation exposure
3200K+C500S+HA50
- - -
Photo response non-uniformity Average dark signal Dark signal non-uniformity Power consumption Output impedance Response1
VOUT = 1 V Light shielding Light shielding
- - - - -
3200K+C500S+HA50
6.86 5.53 3.01 - - -
Response peak
Red Green Blue
Image lag Offset level Output fall delay time Register imbalance Total transfer efficiency Dynamic range
Note
IL VOS td RI TTE DR1 DR2
VOUT = 1 V
- 3.5
t6L = 3 ns VOUT = 1 V VOUT = 1 V, f R = 30 MHz Vsat/DSNU Vsat/ Light shielding
6.0 - 94 - - -1000 -1000
Reset feed-through noise
RFTN1 RFTN2
Light shielding random noise
dark
Bit clamp, t17 > 4 ns
-
Note
td is defined as period from 10% of 2L of VOUT1 to VOUT6, and td is reference data after VOUT1 to VOUT6 pins with FET proving.
Data Sheet S17961EJ2V0DS
5
PD8821
INPUT PIN CAPACITANCE (TA = +25C, VOD = +10 V)
Parameter Shift register clock pin capacitance
Note
Symbol C 1
Pin
Pin No 10 32 15 25 31 9 26 16 7 34
MIN. 235 235 235 235 235 235 235 235 4 4 11 13 190 155 155
TYP. 260 260 260 260 260 260 260 260 5 5 12 15 210 170 170
MAX. 285 285 285 285 285 285 285 285 6 6 13 17 230 185 185
Unit pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF
1AO 1BO 1A 1B
C 2
2AO 2BO 2A 2B
Last stage shift register clock pin capacitance
C 2L
2L R CP TG1 TG2 TG3
Reset gate clock pin capacitance Reset feed-through level clamp clock pin capacitance Transfer gate clock pin capacitance
C R C CP C TG
6 35 24 23 17
Note
C 1, C 2 are equivalent capacitance with driving device, including the co-capacitance between 1 and 2. Pins 10, 15, 25 and 32 ( 1), pins 9, 16, 26 and 31 ( 2), pins 7 and 34 ( 2L), are each connected inside of the device.
Remark
6
Data Sheet S17961EJ2V0DS
TIMING CHART 1 (Bit Clamp Mode)
TG
1
2
2L
R
CP
1 3
25
29
121
123
125
127
5
27
31
119
129
131
7425
7427
7429
7431 132 7426 7428
2
4
6
26
28
30
32
120
122
124
126
128
130
VOUT2, VOUT4, VOUT6
A Note
Optical black
(48 pixels/channel)
Register pixels
Invalid photocell
(3 pixels/channel)
Valid photocell
(3650 pixels/channel)
Invalid photocell
(3 pixels/channel)
(13 pixels/channel)
Note Set the R and CP to low level during this period (A).
7430
7432
7434
Data Sheet S17961EJ2V0DS
VOUT1, VOUT3, VOUT5
7433
PD8821
7
8
t6
90% 10% 90%
TIMING CHART 2 (Bit Clamp Mode)
t7
1
2
t7L
90% 10% 90% 10%
t6L
10%
2L
t9 t8
90% 10% 10%
t10 t17 t15
R
t16
90% 10% 10%
t12 t13 t14
CP
td
Data Sheet S17961EJ2V0DS
VOUT1 to VOUT6 10% VOS
Caution
"10%" and "90%" define as the clock voltage with 5 Vp-p condition. i.e. "10%" shows 0.5 V, "90%" shows 4.5 V
PD8821
PD8821
TIMING CHART 3 (Bit Clamp Mode, Line Clamp Mode)
t2 t3 90% 90% 10% t1 10% t4
TG
1
90% t5 t8 t9 t10 t17 t12 t13 t14
90% t15
R
10%
90% t16
CP
10%
90%
10%
Caution
"10%" and "90%" define as the clock voltage with 5 Vp-p condition. i.e. "10%" shows 0.5 V, "90%" shows 4.5 V
Symbol t1, t5 t2, t4 t3 t6, t7 t6L, t7L t8, t10 t9 t12, t14 t13 t15 t16 t17 t20
MIN. 100 0 500 0 0 0 6 0 8 -3 0 4 5
TYP. 300 10 5000 10 3 3 125 3 125 +250 125 125 125
MAX. 1000 - 20000 - - - 20000 - 20000 +1000 - - -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Data Sheet S17961EJ2V0DS
9
1 3
25
29
121
123
125
127
5
27
31
119
129
131
7429 7425 7427
7431 132 7430
2
4
6
26
28
30
32
120
122
124
126
128
130
VOUT2, VOUT4, VOUT6
A
Optical black
(48 pixels/channel)
Note Invalid photocell
(3 pixels/channel)
Register pixels
Valid photocell
(3650 pixels/channel)
7426
7428
Invalid photocell
(3 pixels/channel)
(13 pixels/channel)
Note Set the R and CP to low level during this period (A).
7432
7434
Data Sheet S17961EJ2V0DS
VOUT1, VOUT3, VOUT5
7433
10
TIMING CHART 4 (Line Clamp Mode)
TG
1
2
2L
R
CP
PD8821
TIMING CHART 5 (Line Clamp Mode)
t6
90% 10% 90%
t7
1
2
t7L
90% 10% 90% 10%
t6L
10%
2L
t8 t9
90% 10% 10%
t10 t20
R
CP
td
Low
Data Sheet S17961EJ2V0DS
VOUT1 to VOUT6 10% VOS
Caution
"10%" and "90%" define as the clock voltage with 5 Vp-p condition. i.e. "10%" shows 0.5 V, "90%" shows 4.5 V
PD8821
11
PD8821
( 1AO, 2AO), ( 1BO, 2BO), ( 1A, 2B), ( 1B, 2B) cross point
1
2
1.5 V or more
1.5 V or more
1AO, 2L & 1BO, 2L cross points
1
2L
1.5 V or more
0 V or more
Remark
Adjust cross points ( 1AO, 2AO) ( 1BO, 2BO) ( 1A, 2A) ( 1B, 2B) and ( 1, 2L) with input resistance of each pin.
1, 2, 2L clock width
Min. 3 ns Min. 4.75 V 4.75 V 4.75 V Min. 3 ns
1AO, 1BO, 1A, 1B 2AO, 2BO, 2A, 2B
Min. 3 ns
2L
2L
Min. 3 ns
1AO, 1BO, 1A, 1B 2AO, 2BO, 2A, 2B
0.25 V Min. 4.75 V 0.25 V
12
Data Sheet S17961EJ2V0DS
PD8821
DEFINITIONS OF CHARACTERISTIC 1. Saturation voltage : Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula, and it is defined by each six of them.
PRNU (%) =
x x
x 100 x : maximum of | xj - x |
3650
xj
j=1
x=
3650
VOUT Register Dark DC level x x
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula, and it is defined by each six of them.
3650
dj
j=1
ADS (mV) =
3650 dj : Dark signal of valid pixel number j
Data Sheet S17961EJ2V0DS
13
PD8821
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula, and it is defined by each six of them.
DSNU (mV) : maximum of | dj - ADS | j = 1 to 3650 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU
6. Output impedance : ZO
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lx*s). Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
TG
Light VOUT
ON
OFF
V1 VOUT
IL (%) = V1 / VOUT x 100
9. Register imbalance : RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels.
RI (%) =
2 n
j=1
(V2j -1 - V2j)
1 n
j=1
n 2
Vj
n
x 100 n : Number of valid pixels Vj : Output voltage of each pixel
14
Data Sheet S17961EJ2V0DS
PD8821
10. Light shielding random noise : dark
Light shielding random noise dark is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling at dark (light shielding).
100
(mV) =
( Vi - V )2
i=1
100
,
V=
1 100 Vi 100 i=1
Vi :A valid pixel output signal among all of the valid pixels for each color.
VOUT
V1
line1
V2
line2
V100
line100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
11. Total transfer efficiently : TTE
The total transfer rate of CCD analog shift register. This is calculated by the following formula, it is defined by each odd output.
TTE(%) = (1-Vb/average output of all the valid pixels) x 100
Vb 7435
Vb: The spilt pixel output (7435th pixel)
7431
7433
Data Sheet S17961EJ2V0DS
15
PD8821
12. Reset feed-through noise: RFTN
RFTN is the switching noise by R and CP, it is defined by each output.
R
CP
2L
+ VOUT1 to VOUT6 - RFTN1 + VOS - RFTN2
16
Data Sheet S17961EJ2V0DS
PD8821
STANDARD CHARACTERISTIC CURVES (1) (Reference Value)
DARK OUTPUT TEMPERATURE CHARACTERISTIC 100 2 STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25C)
Relative Output Voltage
10
1
Relative Output Voltage 0 10 20 30 40 50 60
1
0.2
0.1 Operating Ambient Temperature TA (C)
0.1 1 5 Storage Time (ms) 10
TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter)(TA = 25C)
100%
G
80%
R
B
Response Ration (%)
60%
40%
20%
0% 400
500
600
700
800
Wavelength (nm)
Data Sheet S17961EJ2V0DS
17
PD8821
STANDARD CHARACTERISTIC CURVES (2) (Reference Value)
Power vs. TA (C)
1000 1.10
Response vs. TA (C)
800
600
Response ratio ???
0 10 20 30 40 50 60
1.05
????(mW) Power (mW)
1.00
400
200
0.95
0 ??????TA(?)
0.90 0 10 20 30 40 50 60 ??????TA(?) Operating Ambient Temperature TA (C)
Operating Ambient Temperature TA (C) Offset level vs. TA (C)
4.60 8 7 ????????td(ns) ?????*????(V) Offset level (V) 4.55 6 5 4 3 2 1 4.40 0 10 20 30 40 50 60 ??????TA(?) 0
td vs. TA (C)
4.50
4.45
td (ns)
0
10
20
30
40
50
60
Operating Ambient Temperature TA (C) RFTN1 vs. TA (C)
0
Operating Ambient Temperature TA (C)
??????TA(?)
RFTN1 (mV) ????*????????*????RFTN1(mV)
-100
-200
-300
-400
-500 0 10 20 30 40 50 60 ??????TA(?) Operating Ambient Temperature TA (C)
18
Data Sheet S17961EJ2V0DS
PD8821
APPLICATION CIRCUIT EXAMPLE
+10 V
+
2
0.1 F
47 F/25 V
B4
1 2
VOUT4 GND VOUT6 VOUT5 VOD
VOUT3 GND VOUT1 VOUT2 VOD
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
B3
B6 B5
3 4 5
B1 B2
R 2L
47
6 7
R 2L
GND
CP 2L
GND
47
CP 2L
47
3 3
8 9
47
2BO 1AO
2 2
2BO 1AO
HS-VOD NC NC NC
1BO 2AO
HS-VOD NC NC NC
10 11 12 13 14
2 2
3 3
1BO 2AO
+10 V
+10 V
1A 2B TG3
3
15 2 16 17 18 19 20
1A 2B TG3
GND NC NC
2A 1B TG1 TG2
NC NC
3
3
2 2 2 2
2A 1B TG1 TG2
3
2 2
+5 V B1 to B6 EQUIVALENT CIRCUIT +10 V + + 47 F/25 V
1.5 k
CCD VOUT
10 F/16 V 0.1 F
100 2SA1206
Connects the 3 inverters for each 1 and 2 pin.
Data Sheet S17961EJ2V0DS
19
PD8821
PACKAGE DRAWING
PD8821CZ-A CCD LINEAR IMAGE SENSOR 40-PIN PLASTIC DIP (WITH HEAT SINK) (15.24 mm (600))
(Unit : mm) 94.40.5 94.00.5 1st valid pixel 40 34.70.4
2
21
14.30.3 14.70.3
1 9.750.4 1.270.15 A
1
20
B
6.220.5
15.240.20
B A 0.460.1 0.90.1 SECTION A-A (1.71)
3
10.00.2 11.10.2
5
2.540.25 11.10.2 43.180.4
5
16.670.5 3.00.2 4.00.5 0.250.05
SECTION B-B 7.40.3
7
6
4.510.3 5
4
5 14.10.2
1
5
1 14.80.2
5
Name Glass cap
Dimensions 91.0x11.6x0.7
Refractive index 1.5
1 1st valid pixel The center of the pin1 2 1st valid pixel The center of the package 3 The surface of the CCD chip The top of the cap 4 The bottom of the package The surface of the CCD chip 5 The draft angle of the shaded portions (4 places) are 1 dgree. 6 There is no heat sink exposure from the package. 7 The center of the CCD chip Package side(shaded portion)
40C-1CCD-PKG1
20
Data Sheet S17961EJ2V0DS
PD8821
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device
PD8821CZ-A: CCD linear image sensor 40-pin plastic DIP with heat sink (15.24 mm (600))
Process Partial heating method Conditions Pin temperature: 380C or below, Heat time: 3 seconds or less (per pin).
Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the glass cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of glass cap soiling and heat resistance. So the method cannot be guaranteed.
NOTES OF HANDLING THE PACKAGES
The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. You should not reform the lead frame. We recommend to use a IC-inserter when you assemble to PCB. For this product, the reference value for the three-point bending strength (glass) is bonded to the package body. Note Three-point bending strength test Distance between supports:70mm, Support R:R2mm, Loading
Note
is 280 [N] (at distance between
supports: 70 mm). Avoid imposing a load, however, on the inside portion as viewed from the face on which the window
rate:0.5mm/min.
Load
Load
70 mm
70 mm
Data Sheet S17961EJ2V0DS
21
PD8821
NOTES ON HANDLING THE PACKAGES
1 MOUNTING OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with glass cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating
2 GLASS CAP
Don't either touch glass cap surface by hand or have any object come in contact with glass cap surface. Care should be taken to avoid mechanical or thermal shock because the glass cap is easily to damage. For dirt stuck through electricity ionized air is recommended.
3 OPERATE AND STORAGE ENVIRONMENTS
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
4 ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. 2. 3. 4. 5. 6. Ground the tools such as soldering iron, radio cutting pliers of or pincer. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. Either handle bare handed or use non-chargeable gloves, clothes or material. Ionized air is recommended for discharge when handling CCD image sensor. For the shipment of mounted substrates, use box treated for prevention of static charges. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 M.
22
Data Sheet S17961EJ2V0DS
PD8821
NOTES FOR CMOS DEVICES
1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.
Data Sheet S17961EJ2V0DS
23
PD8821
* The information in this document is current as of July, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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